Master Program (Laurea Magistrale) in Computer Science and Networking

Academic Year 2009-2010

 

High Performance Computing Systems and Enabling Platforms

 

 

Objectives

This course deals with architectures of high-performance computing systems according to several models and approaches, including shared memory multiprocessors, distributed memory multiprocessors and multicomputers, clusters, multiclusters, farms, data centres, and others.

These platforms are studied in terms of architectural model, static and dynamic support to computation and programming models for parallel and distributed processing, performance evaluation, capability for building complex and heterogeneous enabling platforms, also through examples of application cases. Technological features and trends are studied, in particular multi-/many-core technology and high-performance networks.

An initial part of the course is dedicated to review some basic concepts and techniques in computer architecture, in order to render the different backgrounds of students as uniform as possible.

 

Course Program

Part 1 (~ 1/4)

1.      Prerequisites revisited

Processors, memory hierarchies and caching; compiler optimizations, performance parameters; process cooperation and implementation.

2.      Run-time support to concurrency mechanisms

Structured interpretation of process communication and sharing.

Note: the course will adopt a structured approach to the study of computer architecture, according to the style of the basic course in Computer Architecture of the Bachelor Program in Computer Science, University of Pisa. For this reason, as said above, in 1.1 and 1.2 the main concept and techniques of such basic course will be reviewed. The first lecture will discuss the meaning of the structured approach.

3.      Instruction level parallelism

Elements of pipeline and superscalar CPUs, cost models, compiler optimization.

Part 2 (~ 3/4)

4.      Shared memory architectures

SMP, NUMA, and other organizations; interconnection networks; support to concurrency mechanisms, cost models, static and dynamic optimizations; parallel application benchmarks.

5.      Distributed memory architectures

Cluster, MPP, and other organizations; interconnection networks; support to concurrency mechanisms, cost models, static and dynamic optimizations; parallel application benchmarks.

6.      Multicore architectures

Current status and trends of single-chip shared/distributed memory architectures.

 

Course Material

      Notes and other material will be provided through:

www.di.unipi.it/~vannesch, section: Teaching

      Lecture Notes will be provided under the form of

     Slides of lectures

     Documents

      Papers and selected book chapters

      M. Vanneschi, “Architettura degli Elaboratori”, PLUS (Pisa University Press), 2009, in Italian:

     Parts I, II, III of this book contain background concepts and techniques.

     Part IV contains material for this course.

     Since the English version will be ready for the next academic year, some parts will by translated in English during the course, or provided through slides

      Reference Books (optional support/consultation for the exam preparation, or deepening sources):

     D.A. Patterson, J.H. Hennessy, Computer Organization and Design: the Hardware/Software Interface, Morgan Kaufman Publishers Inc.

     D.E. Culler, J.P. Singh, A. Gupta, Parallel Computer Architecture: a Hardware/Software Approach, Morgan Kaufman Publishers Inc.

 

Exam Modality

The exam of High Performance Computing Systems and Enabling Platforms (6 CFU) consists of written + oral test, and an optional report on a given topic.

For all students:

Written test + oral test (in English or in Italian)

Written test: explanation/discussion of concepts and techniques of the course, not necessarily focused on small exercizes. Emphasis will be put on the knowledge of methodologies and their application, as well as on the synthesis capability and on the student’s ability to establish the proper relationships between the various parts of the course.

Optional: a report on a specific topic

Some literature material (e.g. one/some papers) is assigned to the student, e.g. concerning

     existing parallel machines / multicore, or existing projects,

     specific techniques and/or technologies on topics of interest.

Literature for the report is assigned during the first 2-3 weeks of the course.

The assigned material must be studied and interpreted according to the course contents, methodology and approach.

The report must be written in a didactic style, as it were a book chapter for students (“student-proof”).

The report must be submitted a certain time in advance with respect to the exam date.

Registration to take the exam

To take part to a given exam session, the student must register using the the Official Site of Corso di Laurea: http://compass2.di.unipi.it/didattica, section "Laurea Magistrale in Informatica e Netwoking", subsection “orari”.

 

Esame di Architetture Parallele e Distribuite (ASE), Laurea Specialistica, Vecchio Ordinamento

A partire dalla sessione estiva 2009-2010, il programma di esame di ASE (9 CFU) consiste nel programma di "High Performance Computing Systems and Enabling Platforms" (6 CFU) più una parte integrativa di 3 CFU.

Il programma della parte integrativa consiste nelle metodologie e tecniche di parallelizzazione; il materiale didattico è il Cap. X del testo M. Vanneschi, “Architetture degli Elaboratori”, PLUS, 2009.

Le modalità di esame di ASE sono quelle in vigore finora: prova scritta e prova orale, entrambe in italiano.

Nella registrazione ad un appello di esame indicare ASE nelle note.

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COURSE MATERIAL

  1. Course Introduction

    ppt

  2. Prerequisites revisited - Levels

    ppt

  3. Prerequisites revisited - Firmware

    ppt

  4. Prerequisites revisited - Assembler, CPU, and I/O

    ppt

  5. Prerequisites revisited - Memory Hierarchies and Caching

    ppt

  6. Instruction Level Parallelism - Pipelined CPU

    ppt

  7. INTEGRATION TO COURSE MATERIAL and OPTIONAL CONTRIBUTIONS

    Flynn's classification

    Drepper's monograph on Memory Hierarchies

    Survey on Explicit Multithreading

    Cache Coherence Protocols

    Survey on Compiler Transformations

    Multicore Computing state-of-the-art

    Multicore Machines and Programming Models

  8. Run-time support of Interprocess Communication

    ppt

  9. Multiprocessors - Overview

    ppt

  10. Multiprocessors - Interconnection Networks

    ppt

  11. Multiprocessors - Run-time Support of Interprocess Communication

    ppt

  12. Multiprocessors - Multicore architectures

    ppt

  13. Multithreading

    ppt

  14. Clusters

    ppt

  15. Course Conclusion

    ppt

  16. primo appello SPA and ASE : solution outline - final version

  17. primo appello SPA and ASE : results and oral exam dates

  18. secondo appello SPA and ASE : solution outline

  19. secondo appello SPA and ASE : results and oral exam dates

  20. Errata-corrige of slides - version 2

  21. terzo appello SPA and ASE: solution outline

  22. terzo appello: results and oral exam dates: SPA

  23. terzo appello: risultati ASE 

  24. quarto appello SPA and ASE: solution outline

  25. quarto appello: results and oral exam dates: SPA

  26. quarto appello: risultati ASE