References 2003-2006

1. Bernasconi A., Ciriani V., Luccio F., Pagli L., ``Three-Level Logic Minimization Based on Function Regularities'', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(8), pp. 1005-1016, 2003.

2. Ciriani V., ``Synthesis of SPP Three-Level Logic Networks using Affine Spaces'', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(10), pp. 1310-1323, 2003.

3. Ciriani V., ``Three-Level Logic Synthesis: Algebraic Approach and Minimization Algorithms''. Poster at the Ph.D. Forum of VLSI-SoC 2003. Proc. 12th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), page 455, 2003.

4. Ciriani V., Bernasconi A., Drechsler R., ``Testability of SPP Three-Level Logic Networks'', Proc. 12th IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2003), pp. 331-336, 2003.

5. Ciriani V., Luccio F., Pagli L., ``Synthesis of Integer Multipliers in Sum of Pseudoproducts Form'', Integration - the VLSI Journal, 36(3), pp. 103-118, 2003.

6. Bernasconi A., Ciriani V., Luccio F., Pagli L., ``Exploiting Regularities for Boolean Function Synthesis'', Theory of Computing Systems, 39(4), pp. 485-501, 2006.

7. Bernasconi A., Ciriani V., ``DSOP: Synthesis of a new class of regular functions''. Proc. 9th Euromicro Conference on Digital Systems Design: Architectures, Methods and Tools, 2006.

8. Bernasconi A., Ciriani V., Cordone, R., ``EXOR Projected Sum of Products''. Proc. 14th International Conference on Very Large Scale Integration (VLSI-SoC), 2006.

9. Bernasconi A., Ciriani V., Drechsler R., Villa T., ``Efficient Minimization of Fully Testable 2-SPP Networks''. Proc. International Conference on Design, Automation and Test in Europe (DATE), 2006.

10. Ciriani V., Bernasconi A., Drechsler R., ``Testability of SPP Three-Level Logic Networks in Static Fault Models'', Invited chapter in VLSI-SOC: From Systems to Chips, M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking (Eds.), Kluwer-Springer, 2006, ISBN: 0-387-33402-5.

11. Ciriani V., Bernasconi A., Drechsler R., ``Testability of SPP Three-Level Logic Networks in Static Fault Models''. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, to appear, 2006.